Embodiments of the inventive concept relate to data writing devices incorporate into memory linked architectures. More particularly, embodiments of the inventive concept relate to data writing devices for memory linked architectures that are capable of providing improved data writing speeds. Other embodiments of the inventive concept relate to methods of operating a data writing device within memory linked architectures.
FIG. 1 is a block diagram illustrating in relevant part a data system. Referring to FIG. 1, a data system 100 comprises a Read Only Memory (ROM) writer 110 arranged in relation to a plurality of memory socket assemblies 120-1 to 120-m, each including a socket adapted to mount a memory device. That is, each socket may be used to mechanically and electrically connect a corresponding memory link architecture (MLA) configured to receive data (e.g., image data) as conventionally written by the ROM writer 110.
For example, the ROM writer 110 may selectively write “image data” in preparation for execution of an application by a host CPU (not shown). Image data may include, for example, Operating System (OS) image data, a boot program, a boot loader, flash translation layer (FTL) code, and other programming code necessary to operation of the memory link architectures respectively associated with the memory socket assemblies 121-1 to 121-m. 
The ROM writer 110 comprises a CPU 111, a primary memory 112, and a plurality of control devices 113-1 to 113-m. During an operation designed to transfer image data from the ROM writer 110 to the MLAs of the plurality of memory socket assemblies 121-1 to 121-m-1 to 120, the ROM writer is solely used to accomplish said transfer.
Thus, each MLA must be downloaded with image data in sequence using the ROM writer 110 once all of the MLAs have been mounted in their respective sockets. This requires a rather large block of time during which nothing else can happen as the memory system is being configured. That is, the CPU 111 of the ROM writer 110 is only able to write image data on a write operation by write operation basis in relation to multiplicity of connected MLAs, and only after that are all mounted. As the number of MLAs increases within a particular host device, the associated delay in MLA download configuration only increases. Accordingly, some method of improving the speed of data download to a number of memory link architectures is needed.